Design Methodology of Reusable VLSI Subsystems

Funding

CICYT.

Duration

December 1999 to December 2002

Summary

Advances in submicron technologies have resulted in the integration of complete systems into a single chip, the so-called SOC (System-On-Chip). However, current methodologies and design tools are considered as inefficient to develop the new ASIC paradigm. The required productivity increase, necessary to equalize the gate density explotion allowed by current tecnology, is not supported by neither current tools nor methodologies. The use of predesigned and preverified functional blocks (cores) allows the integration of systems into ASICs in the same way as current systems are designed on printed circuits boards. The aim of this project is two-folded: on one hand, to establish a design methodology of reusable subsystems and, on the other hand, to adapt the current ASIC design methodology to the new use of these subsystems. To verify the methodology, a video coding application has been selected as main target. In addition, since video coding applications have attracted recently great interest in industrial sectors, the target application would likely become a project contribution.